1. Field of the Invention
The present invention relates to a data transfer circuit. More particularly, the present invention relates to a data transfer circuit which transfers input data toward a target object having a bit width different from a bit width of the input data.
2. Description of the Related Art
According to one example of this type of circuit, a buffer group contains a plurality of. FIFO-type buffers, each of which has a bit width larger than a client data width. In order to read out and write data from and into such a buffer group, a command decode circuit issues a command and an address that are based on an address and a command received from a master device, toward a memory device. Access to the memory device is executed by using a burst length previously set according to a bus width of the memory device. Thereby, the bus width of the memory device can be easily changed, and a band width can be effectively used in an architecture in which the burst access is taken into consideration.
However, in the above-described circuit, in order to read out and write the data, the plurality of FIFO-type buffers, each of which has the bit width larger than the client data width are utilized. Thus, in the above-described circuit, there is a potential risk that a circuit scale is increased.